renesas: initial porting for UNO R4
Tested on Nexopixel-like (clockless)
This commit is contained in:
Martino Facchin
parent
4c5738ce40
commit
b1f3a6613e
@ -46,6 +46,8 @@
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#elif defined(ARDUINO_ARCH_APOLLO3)
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// Apollo3 platforms (e.g. the Ambiq Micro Apollo3 Blue as used by the SparkFun Artemis platforms)
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#include "platforms/apollo3/led_sysdefs_apollo3.h"
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#elif defined(ARDUINO_ARCH_RENESAS) || defined(ARDUINO_ARCH_RENESAS_UNO) || defined(ARDUINO_ARCH_RENESAS_PORTENTA)
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#include "platforms/arm/renesas/led_sysdef_arm_renesas.h"
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#else
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//
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// We got here because we don't recognize the platform that you're
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@ -42,6 +42,8 @@
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#include "platforms/esp/32/fastled_esp32.h"
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#elif defined(ARDUINO_ARCH_APOLLO3)
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#include "platforms/apollo3/fastled_apollo3.h"
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#elif defined(ARDUINO_ARCH_RENESAS) || defined(ARDUINO_ARCH_RENESAS_UNO) || defined(ARDUINO_ARCH_RENESAS_PORTENTA)
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#include "platforms/arm/renesas/fastled_arm_renesas.h"
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#else
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// AVR platforms
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#include "platforms/avr/fastled_avr.h"
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128
src/platforms/arm/renesas/clockless_arm_renesas.h
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128
src/platforms/arm/renesas/clockless_arm_renesas.h
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@ -0,0 +1,128 @@
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#ifndef __INC_CLOCKLESS_ARM_RENESAS
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#define __INC_CLOCKLESS_ARM_RENESAS
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FASTLED_NAMESPACE_BEGIN
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// Definition for a single channel clockless controller for RA4M1 (Cortex M4)
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// See clockless.h for detailed info on how the template parameters are used.
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#define ARM_DEMCR (*(volatile uint32_t *)0xE000EDFC) // Debug Exception and Monitor Control
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#define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks
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#define ARM_DWT_CTRL (*(volatile uint32_t *)0xE0001000) // DWT control register
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#define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count
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#define ARM_DWT_CYCCNT (*(volatile uint32_t *)0xE0001004) // Cycle count register
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#define FASTLED_HAS_CLOCKLESS 1
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template <int DATA_PIN, int T1, int T2, int T3, EOrder RGB_ORDER = RGB, int XTRA0 = 0, bool FLIP = false, int WAIT_TIME = 50>
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class ClocklessController : public CPixelLEDController<RGB_ORDER> {
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typedef typename FastPin<DATA_PIN>::port_ptr_t data_ptr_t;
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typedef typename FastPin<DATA_PIN>::port_t data_t;
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data_t mPinMask;
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data_ptr_t mPort;
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CMinWait<WAIT_TIME> mWait;
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public:
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virtual void init() {
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FastPin<DATA_PIN>::setOutput();
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mPinMask = FastPin<DATA_PIN>::mask();
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mPort = FastPin<DATA_PIN>::port();
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}
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virtual uint16_t getMaxRefreshRate() const { return 400; }
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protected:
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virtual void showPixels(PixelController<RGB_ORDER> & pixels) {
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mWait.wait();
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if(!showRGBInternal(pixels)) {
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sei(); delayMicroseconds(WAIT_TIME); cli();
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showRGBInternal(pixels);
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}
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mWait.mark();
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}
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template<int BITS> __attribute__ ((always_inline)) inline static void writeBits(FASTLED_REGISTER uint32_t & next_mark, FASTLED_REGISTER data_ptr_t port, FASTLED_REGISTER data_t hi, FASTLED_REGISTER data_t lo, FASTLED_REGISTER uint8_t & b) {
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for(FASTLED_REGISTER uint32_t i = BITS-1; i > 0; --i) {
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while(ARM_DWT_CYCCNT < next_mark);
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next_mark = ARM_DWT_CYCCNT + (T1+T2+T3);
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FastPin<DATA_PIN>::fastset(port, hi);
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if(b&0x80) {
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while((next_mark - ARM_DWT_CYCCNT) > (T3+(2*(F_CPU/24000000))));
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FastPin<DATA_PIN>::fastset(port, lo);
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} else {
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while((next_mark - ARM_DWT_CYCCNT) > (T2+T3+(2*(F_CPU/24000000))));
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FastPin<DATA_PIN>::fastset(port, lo);
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}
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b <<= 1;
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}
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while(ARM_DWT_CYCCNT < next_mark);
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next_mark = ARM_DWT_CYCCNT + (T1+T2+T3);
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FastPin<DATA_PIN>::fastset(port, hi);
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if(b&0x80) {
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while((next_mark - ARM_DWT_CYCCNT) > (T3+(2*(F_CPU/24000000))));
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FastPin<DATA_PIN>::fastset(port, lo);
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} else {
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while((next_mark - ARM_DWT_CYCCNT) > (T2+T3+(2*(F_CPU/24000000))));
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FastPin<DATA_PIN>::fastset(port, lo);
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}
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}
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// This method is made static to force making register Y available to use for data on AVR - if the method is non-static, then
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// gcc will use register Y for the this pointer.
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static uint32_t showRGBInternal(PixelController<RGB_ORDER> pixels) {
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// Get access to the clock
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ARM_DEMCR |= ARM_DEMCR_TRCENA;
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ARM_DWT_CTRL |= ARM_DWT_CTRL_CYCCNTENA;
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ARM_DWT_CYCCNT = 0;
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FASTLED_REGISTER data_ptr_t port = FastPin<DATA_PIN>::port();
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FASTLED_REGISTER data_t hi = *port | FastPin<DATA_PIN>::mask();
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FASTLED_REGISTER data_t lo = *port & ~FastPin<DATA_PIN>::mask();
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*port = lo;
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// Setup the pixel controller and load/scale the first byte
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pixels.preStepFirstByteDithering();
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FASTLED_REGISTER uint8_t b = pixels.loadAndScale0();
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cli();
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uint32_t next_mark = ARM_DWT_CYCCNT + (T1+T2+T3);
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while(pixels.has(1)) {
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pixels.stepDithering();
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#if (FASTLED_ALLOW_INTERRUPTS == 1)
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cli();
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// if interrupts took longer than 45µs, punt on the current frame
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if(ARM_DWT_CYCCNT > next_mark) {
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if((ARM_DWT_CYCCNT-next_mark) > ((WAIT_TIME-INTERRUPT_THRESHOLD)*CLKS_PER_US)) { sei(); return 0; }
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}
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hi = *port | FastPin<DATA_PIN>::mask();
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lo = *port & ~FastPin<DATA_PIN>::mask();
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#endif
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// Write first byte, read next byte
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writeBits<8+XTRA0>(next_mark, port, hi, lo, b);
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b = pixels.loadAndScale1();
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// Write second byte, read 3rd byte
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writeBits<8+XTRA0>(next_mark, port, hi, lo, b);
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b = pixels.loadAndScale2();
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// Write third byte, read 1st byte of next pixel
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writeBits<8+XTRA0>(next_mark, port, hi, lo, b);
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b = pixels.advanceAndLoadAndScale0();
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#if (FASTLED_ALLOW_INTERRUPTS == 1)
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sei();
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#endif
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};
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sei();
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return ARM_DWT_CYCCNT;
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}
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};
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FASTLED_NAMESPACE_END
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#endif
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8
src/platforms/arm/renesas/fastled_arm_renesas.h
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8
src/platforms/arm/renesas/fastled_arm_renesas.h
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@ -0,0 +1,8 @@
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#ifndef __INC_FASTLED_ARM_RENESAS_H
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#define __INC_FASTLED_ARM_RENESAS_H
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#include "fastpin_arm_renesas.h"
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#include "../../fastspi_ardunio_core.h"
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#include "clockless_arm_renesas.h"
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#endif
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105
src/platforms/arm/renesas/fastpin_arm_renesas.h
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105
src/platforms/arm/renesas/fastpin_arm_renesas.h
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#ifndef __INC_FASTPIN_ARM_RENESAS_H
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#define __INC_FASTPIN_ARM_RENESAS_H
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FASTLED_NAMESPACE_BEGIN
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#if defined(FASTLED_FORCE_SOFTWARE_PINS)
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#warning "Software pin support forced, pin access will be slightly slower."
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#define NO_HARDWARE_PIN_SUPPORT
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#undef HAS_HARDWARE_PIN_SUPPORT
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#else
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#include "bsp_api.h"
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/// Template definition for STM32 style ARM pins, providing direct access to the various GPIO registers. Note that this
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/// uses the full port GPIO registers. In theory, in some way, bit-band register access -should- be faster, however I have found
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/// that something about the way gcc does register allocation results in the bit-band code being slower. It will need more fine tuning.
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/// The registers are data output, set output, clear output, toggle output, input, and direction
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template<uint8_t PIN, bsp_io_port_pin_t bspPin, uint32_t _PORT> class _ARMPIN {
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public:
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typedef volatile uint16_t * port_ptr_t;
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typedef uint16_t port_t;
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#define PORT ((R_PORT0_Type*)(_PORT))
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#define digitalBspPinToPort(P) (P >> 8)
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#define digitalBspPinToBitMask(P) (1 << (P & 0xFF))
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#if 0
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inline static void setOutput() {
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if(_BIT<8) {
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_CRL::r() = (_CRL::r() & (0xF << (_BIT*4)) | (0x1 << (_BIT*4));
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} else {
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_CRH::r() = (_CRH::r() & (0xF << ((_BIT-8)*4))) | (0x1 << ((_BIT-8)*4));
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}
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}
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inline static void setInput() { /* TODO */ } // TODO: preform MUX config { _PDDR::r() &= ~_MASK; }
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#endif
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inline static void setOutput() { pinMode(PIN, OUTPUT); } // TODO: perform MUX config { _PDDR::r() |= _MASK; }
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inline static void setInput() { pinMode(PIN, INPUT); } // TODO: preform MUX config { _PDDR::r() &= ~_MASK; }
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inline static void hi() __attribute__ ((always_inline)) { PORT->POSR = digitalBspPinToBitMask(bspPin); }
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inline static void lo() __attribute__ ((always_inline)) { PORT->PORR = digitalBspPinToBitMask(bspPin); }
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inline static void set(FASTLED_REGISTER port_t val) __attribute__ ((always_inline)) { PORT->PODR = val; }
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inline static void strobe() __attribute__ ((always_inline)) { toggle(); toggle(); }
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inline static void toggle() __attribute__ ((always_inline)) { PORT->PODR & digitalBspPinToBitMask(bspPin) ? lo() : hi(); }
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inline static void hi(FASTLED_REGISTER port_ptr_t port) __attribute__ ((always_inline)) { hi(); }
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inline static void lo(FASTLED_REGISTER port_ptr_t port) __attribute__ ((always_inline)) { lo(); }
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inline static void fastset(FASTLED_REGISTER port_ptr_t port, FASTLED_REGISTER port_t val) __attribute__ ((always_inline)) { *port = val; }
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inline static port_t hival() __attribute__ ((always_inline)) { return PORT->PODR | digitalBspPinToBitMask(bspPin); }
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inline static port_t loval() __attribute__ ((always_inline)) { return PORT->PODR & ~digitalBspPinToBitMask(bspPin); }
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inline static port_ptr_t port() __attribute__ ((always_inline)) { return &PORT->PODR; }
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inline static port_ptr_t sport() __attribute__ ((always_inline)) { return &PORT->POSR; }
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inline static port_ptr_t cport() __attribute__ ((always_inline)) { return &PORT->PORR; }
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inline static port_t mask() __attribute__ ((always_inline)) { return digitalBspPinToBitMask(bspPin); }
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};
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#define _FL_DEFPIN(PIN, bspPin, PORT) template<> class FastPin<PIN> : public _ARMPIN<PIN, bspPin, PORT> {};
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// Actual pin definitions
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#if defined(ARDUINO_UNOR4_WIFI)
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#define MAX_PIN 21
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// D0-D13
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_FL_DEFPIN( 0, BSP_IO_PORT_03_PIN_01, R_PORT3_BASE ); _FL_DEFPIN( 1, BSP_IO_PORT_03_PIN_02, R_PORT3_BASE ); _FL_DEFPIN( 2, BSP_IO_PORT_01_PIN_04, R_PORT1_BASE );
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_FL_DEFPIN( 3, BSP_IO_PORT_01_PIN_05, R_PORT1_BASE ); _FL_DEFPIN( 4, BSP_IO_PORT_01_PIN_06, R_PORT1_BASE ); _FL_DEFPIN( 5, BSP_IO_PORT_01_PIN_07, R_PORT1_BASE );
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_FL_DEFPIN( 6, BSP_IO_PORT_01_PIN_11, R_PORT1_BASE ); _FL_DEFPIN( 7, BSP_IO_PORT_01_PIN_12, R_PORT1_BASE ); _FL_DEFPIN( 8, BSP_IO_PORT_03_PIN_04, R_PORT3_BASE );
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_FL_DEFPIN( 9, BSP_IO_PORT_03_PIN_03, R_PORT3_BASE ); _FL_DEFPIN(10, BSP_IO_PORT_01_PIN_03, R_PORT1_BASE ); _FL_DEFPIN(11, BSP_IO_PORT_04_PIN_11, R_PORT4_BASE );
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_FL_DEFPIN(12, BSP_IO_PORT_04_PIN_10, R_PORT4_BASE ); _FL_DEFPIN(13, BSP_IO_PORT_01_PIN_02, R_PORT1_BASE );
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// A0-A5
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_FL_DEFPIN(14, BSP_IO_PORT_00_PIN_14, R_PORT0_BASE ); _FL_DEFPIN(15, BSP_IO_PORT_00_PIN_00, R_PORT0_BASE ); _FL_DEFPIN(16, BSP_IO_PORT_00_PIN_01, R_PORT0_BASE );
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_FL_DEFPIN(17, BSP_IO_PORT_00_PIN_02, R_PORT0_BASE ); _FL_DEFPIN(18, BSP_IO_PORT_01_PIN_01, R_PORT1_BASE ); _FL_DEFPIN(19, BSP_IO_PORT_01_PIN_00, R_PORT1_BASE );
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#elif defined(ARDUINO_UNOR4_MINIMA)
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#define MAX_PIN 21
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// D0-D13
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_FL_DEFPIN( 0, BSP_IO_PORT_03_PIN_01, R_PORT3_BASE ); _FL_DEFPIN( 1, BSP_IO_PORT_03_PIN_02, R_PORT3_BASE ); _FL_DEFPIN( 2, BSP_IO_PORT_01_PIN_05, R_PORT1_BASE );
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_FL_DEFPIN( 3, BSP_IO_PORT_01_PIN_04, R_PORT1_BASE ); _FL_DEFPIN( 4, BSP_IO_PORT_01_PIN_03, R_PORT1_BASE ); _FL_DEFPIN( 5, BSP_IO_PORT_01_PIN_02, R_PORT1_BASE );
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_FL_DEFPIN( 6, BSP_IO_PORT_01_PIN_06, R_PORT1_BASE ); _FL_DEFPIN( 7, BSP_IO_PORT_01_PIN_07, R_PORT1_BASE ); _FL_DEFPIN( 8, BSP_IO_PORT_03_PIN_04, R_PORT3_BASE );
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_FL_DEFPIN( 9, BSP_IO_PORT_03_PIN_03, R_PORT3_BASE ); _FL_DEFPIN(10, BSP_IO_PORT_01_PIN_12, R_PORT1_BASE ); _FL_DEFPIN(11, BSP_IO_PORT_01_PIN_09, R_PORT1_BASE );
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_FL_DEFPIN(12, BSP_IO_PORT_01_PIN_10, R_PORT1_BASE ); _FL_DEFPIN(13, BSP_IO_PORT_01_PIN_11, R_PORT1_BASE );
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// A0-A5
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_FL_DEFPIN(14, BSP_IO_PORT_00_PIN_14, R_PORT0_BASE ); _FL_DEFPIN(15, BSP_IO_PORT_00_PIN_00, R_PORT0_BASE ); _FL_DEFPIN(16, BSP_IO_PORT_00_PIN_01, R_PORT0_BASE );
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_FL_DEFPIN(17, BSP_IO_PORT_00_PIN_02, R_PORT0_BASE ); _FL_DEFPIN(18, BSP_IO_PORT_01_PIN_01, R_PORT1_BASE ); _FL_DEFPIN(19, BSP_IO_PORT_01_PIN_00, R_PORT1_BASE );
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#endif
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#define SPI_DATA 12
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#define SPI_CLOCK 13
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#define HAS_HARDWARE_PIN_SUPPORT 1
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#endif // FASTLED_FORCE_SOFTWARE_PINS
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FASTLED_NAMESPACE_END
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#endif // __INC_FASTPIN_ARM_RENESAS_H
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28
src/platforms/arm/renesas/led_sysdef_arm_renesas.h
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28
src/platforms/arm/renesas/led_sysdef_arm_renesas.h
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@ -0,0 +1,28 @@
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#ifndef __INC_LED_SYSDEFS_ARM_RENESAS_H
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#define __INC_LED_SYSDEFS_ARM_RENESAS_H
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#define FASTLED_ARM
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#ifndef INTERRUPT_THRESHOLD
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#define INTERRUPT_THRESHOLD 1
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#endif
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// Default to allowing interrupts
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#ifndef FASTLED_ALLOW_INTERRUPTS
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#define FASTLED_ALLOW_INTERRUPTS 1
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#endif
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#if FASTLED_ALLOW_INTERRUPTS == 1
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#define FASTLED_ACCURATE_CLOCK
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#endif
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// reusing/abusing cli/sei defs for due
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#define cli() __disable_irq();
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#define sei() __enable_irq();
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#define FASTLED_NO_PINMAP
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typedef volatile uint32_t RoReg;
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typedef volatile uint32_t RwReg;
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#endif
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