1d4487b6cd
* Improved pin manager, ethernet config * Ethernet is configured prior even to LED pins * Pin Manager allocation / deallocation functions now take an "ownership" tag parameter, helping avoid accidentally free'ing pins that were allocated by other code * Pin Manager now has ability to allocate multiple pins at once; Simplifies error handling * Fix operator precedence error Bitwise AND has lower precedence than the relational "greater than" operator. * PinManager update for some user modules * don't build everything... * Final step to reduce RAM overhead * update comment * remove macros * Remove leftover allocated * Init ethernet after settings saved Co-authored-by: Christian Schwinne <dev.aircoookie@gmail.com>
110 lines
3.9 KiB
C
110 lines
3.9 KiB
C
#ifndef WLED_ETHERNET_H
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#define WLED_ETHERNET_H
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#ifdef WLED_USE_ETHERNET
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#include "pin_manager.h"
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// The following six pins are neither configurable nor
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// can they be re-assigned through IOMUX / GPIO matrix.
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// See https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-ethernet-kit-v1.1.html#ip101gri-phy-interface
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const managed_pin_type esp32_nonconfigurable_ethernet_pins[6] = {
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{ 21, true }, // RMII EMAC TX EN == When high, clocks the data on TXD0 and TXD1 to transmitter
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{ 19, true }, // RMII EMAC TXD0 == First bit of transmitted data
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{ 22, true }, // RMII EMAC TXD1 == Second bit of transmitted data
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{ 25, false }, // RMII EMAC RXD0 == First bit of received data
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{ 26, false }, // RMII EMAC RXD1 == Second bit of received data
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{ 27, true }, // RMII EMAC CRS_DV == Carrier Sense and RX Data Valid
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};
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// For ESP32, the remaining five pins are at least somewhat configurable.
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// eth_address is in range [0..31], indicates which PHY (MAC?) address should be allocated to the interface
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// eth_power is an output GPIO pin used to enable/disable the ethernet port (and/or external oscillator)
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// eth_mdc is an output GPIO pin used to provide the clock for the management data
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// eth_mdio is an input/output GPIO pin used to transfer management data
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// eth_type is the physical ethernet module's type (ETH_PHY_LAN8720, ETH_PHY_TLK110)
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// eth_clk_mode defines the GPIO pin and GPIO mode for the clock signal
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// However, there are really only four configurable options on ESP32:
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// ETH_CLOCK_GPIO0_IN == External oscillator, clock input via GPIO0
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// ETH_CLOCK_GPIO0_OUT == ESP32 provides 50MHz clock output via GPIO0
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// ETH_CLOCK_GPIO16_OUT == ESP32 provides 50MHz clock output via GPIO16
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// ETH_CLOCK_GPIO17_OUT == ESP32 provides 50MHz clock output via GPIO17
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typedef struct EthernetSettings {
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uint8_t eth_address;
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int eth_power;
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int eth_mdc;
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int eth_mdio;
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eth_phy_type_t eth_type;
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eth_clock_mode_t eth_clk_mode;
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} ethernet_settings;
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ethernet_settings ethernetBoards[] = {
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// None
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{
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},
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// WT32-EHT01
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// (*) NOTE: silkscreen on board revision v1.2 may be wrong:
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// silkscreen on v1.2 says IO35, but appears to be IO5
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// silkscreen on v1.2 says RXD, and appears to be IO35
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{
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1, // eth_address,
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16, // eth_power,
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23, // eth_mdc,
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18, // eth_mdio,
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ETH_PHY_LAN8720, // eth_type,
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ETH_CLOCK_GPIO0_IN // eth_clk_mode
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},
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// ESP32-POE
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{
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0, // eth_address,
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12, // eth_power,
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23, // eth_mdc,
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18, // eth_mdio,
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ETH_PHY_LAN8720, // eth_type,
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ETH_CLOCK_GPIO17_OUT // eth_clk_mode
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},
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// WESP32
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{
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0, // eth_address,
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-1, // eth_power,
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16, // eth_mdc,
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17, // eth_mdio,
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ETH_PHY_LAN8720, // eth_type,
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ETH_CLOCK_GPIO0_IN // eth_clk_mode
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},
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// QuinLed-ESP32-Ethernet
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{
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0, // eth_address,
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5, // eth_power,
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23, // eth_mdc,
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18, // eth_mdio,
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ETH_PHY_LAN8720, // eth_type,
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ETH_CLOCK_GPIO17_OUT // eth_clk_mode
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},
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// TwilightLord-ESP32 Ethernet Shield
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{
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0, // eth_address,
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5, // eth_power,
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23, // eth_mdc,
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18, // eth_mdio,
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ETH_PHY_LAN8720, // eth_type,
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ETH_CLOCK_GPIO17_OUT // eth_clk_mode
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},
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// ESP3DEUXQuattro
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{
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1, // eth_address,
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-1, // eth_power,
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23, // eth_mdc,
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18, // eth_mdio,
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ETH_PHY_LAN8720, // eth_type,
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ETH_CLOCK_GPIO17_OUT // eth_clk_mode
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}
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};
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#endif
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#endif |